The present invention is in the field of flash memory. More particularly, the present invention provides a method, apparatus, and system to enhance negative voltage switching.
The design of memory support circuitry can determine the competitiveness of a memory device. Memory must be fast, low power, and physically compact data storage to remain competitive. Memory access time is a measure used to how fast the memory is and can be based on the speed of operations such as programming, erasing, and reading. These operations, in turn, can be limited by the physical configuration of the memory. In flash memory, for example, memory cells are transistors and the transistors are typically organized in blocks having rows and columns. Transistors in a row may have their gates coupled to a conductor called a word line. The sources of these transistors may be coupled to a source line. Transistors in a column may have their drains connected in columns by bit lines, but usually not to drains of transistors in the same row. Further, a number of these rows and columns of memory cells are divided into blocks. Source lines may describe blocks because all the source lines in a block may be coupled such that a voltage applied to the source line is applied to the source of all the memory cells in that block. Since alternate transistor configurations may switch the roles of the drain and source in any type of circuitry, drain/source sometimes refers to a first element of a transistor coupled to the transistor""s channel and source/drain refers to a second element coupled to the other side of that transistor""s channel. Programming, erasing, and reading are limited by this physical configuration because voltages applied to one memory cell are also applied to other memory cells in the block. Thus, to perform an operation on a memory cell, a process called latching selects the memory cell by applying program-mode, erase-mode, or read-mode signals to the selected memory cell and applying signals to deselected memory cells to prevent corruption of their contents.
Programming a memory cell refers to storing a charge on a capacitance of the memory cell. The amount of charge on the capacitance can be directly related to the threshold voltage of the memory cell. In flash memory, for example, the transistors have a capacitance in the form of floating gates separated from the gate and the substrate by dielectric layers. When a memory cell is selected for programming, an address indicating the physical location of the selected memory cell is transmitted to a memory array controller. The memory array controller also receives data to program into the selected memory cell. The memory array controller can latch the selected memory cell, applying program-mode signals to the selected word line, source line, and bit line coupled to the memory cell such as twelve, zero, and seven volts, respectively. Program-mode signals are typically voltages that may be applied to a memory cell so the memory cell can be programmed. Program-mode voltages can vary depending upon the design of a memory cell and the memory array configuration. Then, the memory array controller can program the selected memory cell by applying a voltage pulse to the selected bit line, e.g. the drain/source. Voltage pulses applied to the drain/source cause a charge to build up on the floating gate. The floating gate is charged by hot electron injection or by hot hole injection when a voltage pulse is applied to the drain/source. Since programming requires voltages on the bit line (a column) and the word line (a row), a single transistor can be latched and programmed.
Unlike programming, selecting memory cells to be erased is typically done by selecting rows of memory cells because erasing can be performed by applying an erase-mode signal having a negative word line to source line voltage. Erase-mode signals supply a voltage and sometimes a current, both of which may vary in accordance with memory cell attributes and the memory array configuration, and are designed to reduce a charge on a memory cell. Some memory configurations remove charges by applying zero volts to the word line and twelve volts to the source line of the selected memory cells. In many transistors, applying more than twelve volts to the source line can place the transistor in a break down mode, a mode that is detrimental to the lifetime cycles of the memory. However, greater voltage differences between the selected word line and the source line accomplished with a negative voltage on the selected word line can remove the charge from the floating gates more quickly without causing the transistors to move into a break down mode. Therefore, other memory designs employ a negative voltage switch to apply a negative voltage to the selected word line.
Reading a selected memory cell, when the memory cell is a transistor, may be accomplished by applying read-mode signals and comparing a current between the drain and source of the transistor to a reference. Read-mode signals may comprise one volt applied to the selected bit line, five volts applied to the selected word line and zero volts applied to the selected source line.
A negative charge pump, negative voltage switch, and positive voltage switch can supply the signals for selected and deselected memory cells. A negative charge pump may supply an erase-mode signal to the negative voltage switch when a block coupled to the negative charge pump comprises a selected memory cell to erase. A positive voltage switch may supply a normal operating voltage to the negative voltage switch. The negative voltage switch is typically coupled to a word line driver and can either provide the erase-mode signal to a memory cell selected for erasure or the normal operating voltage to memory cells not selected for erasure. Although negative voltage switches can supply the voltages to the selected and deselected memory cells, the negative charge pump, when used in conjunction with these negative voltage switches, can limit the size and operation of the storage devices. First, negative charge pumps may be limited to supply currents in the range of 50 microamperes since larger currents require more layout area and more power consumption. Several of the negative voltage switches coupled to these negative charge pumps use power when supplying voltages to deselected memory cells, limiting the memory device to a maximum data storage capacity. For example, a negative charge pump limited to 50 microamperes may supply up to 25 blocks of deselected memory cells if each negative voltage switch burned two microamperes. Second, negative voltage switches may not support alternate memory operations such as providing a read-mode signal for reading while receiving a negative voltage for erasing, or providing a read-mode signal for reading while providing a program-mode signal for programming. Finally, some of these negative voltage switches are limited to supply a low magnitude, negative voltage for erasing.